One time programmable (OTP) and multi-time programmable (MTP) memories have been recently introduced for beneficial use in a number of applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing ID, security ID, and many other applications. These devices now occupy an important segment of the Non-volatile Memory market and applications.
In addition OTP and MTP devices are optimal choices for extremely low cost, fast solid state random access memory for write once, read-many applications. The savings in cost are derived chiefly by the removal of overhead required to support the erase operation. This is particularly important for maturing services such as social networks and other platforms that are heavy users of multi-media data that is created and stored, but then rarely changed (i.e., pictures, audio, videos, etc.) The archiving of these massive data necessitates a low cost flash memory that are stripped of any traditional cumbersome overhead, yet still maintain the ability to support low number of re-write.
Traditionally, OTP devices are implemented with either EPROM device structures or antifuse structures, where the devices are designed to be (and can be) single bit and programmed only once. The most commonly used EPROM structure is typically a floating gate storage device where electrons are injected and stored on the floating gate. The injection mechanism for programming can either be channel hot electron injection or Fowler-Nordheim electron tunneling. The advantage of these OTP implementations is that they are CMOS/logic compatible, and usually require very few additional masking/processing steps. In most instances, since an integrated circuit includes a high voltage driver component, the floating gate oxide manufacturing can be integrated as part of a high voltage I/O transistor processing module.
An OTP memory array offers simple non-volatile data storage on integrated circuits. The low cost of implementing an OTP makes it a good solution for applications that rarely (or never) require re-programming of the stored data. The low cost of current OTP implementations mainly comes from the fact that no complicated schemes and support circuitry are required to facilitate an erase operation. That is, a typical erase operation would require voltage of opposite polarities, as compared to a programming operation. This is especially true for a NVM device that is implemented with storage of injected electrons unto a floating gate.
While OTP devices are useful in many applications, there are other high-value applications requiring multi-time programmable (MTP) memory that can provide the ability for the device to be updated. Among other reasons, some devices become degraded from aging or changes in their operating environment. In addition some applications may benefit from so-called multi-level or multi-bit capability in which the state of a cell can be set to something more than just two states, including in some instances an odd number of states. Thus, for example it may become necessary to re-calibrate and re-trim a mixed signal circuit like a high-performance DAC that is frequently are integrated in today's complex SoCs. Other examples known in the art, including access key revocation, upgrading to code revisions, periodic data logging, etc. also benefit from few-time or multi-time programmable capability.
MTP memory, such as EEPROM or flash memory, is repeatedly programmable to update data, and has specific circuits for erasing, programming, and reading operations. Unlike MTP memory, OTP memory does not use an erasing circuit, so the circuit for controlling the operations of the OTP memory is simpler than the circuit for controlling the operations of the MTP memory, even though it lacks multi-programmable capability. To emulate a multi-time programmable array and implement more than one programming/erase cycle, the prior art is limited typically to an OTP redundancy scheme that mimics multiple programming features. That is, a separate OTP array with separate cells is programmed for each cycle. An example of this is offered by Kilopass under the trade name Itera. In that approach a memory block there consists of a memory array and analog and digital circuits including high voltage switches, charge pump, bandgap, controller, etc. The memory array is partitioned in into separate sub-arrays, one for each desired program cycle. Thus when the device is programmed for the first time, a controller writes to the first sub-array and when the device is reprogrammed, the controller writes to the second sub-array and so on. In essence, one or more completely redundant arrays of cells is used for each time the array needs to be updated. While these cells are small, this scheme costs additional silicon real estate.
Thus it is desirable to have a new type of OTP device that can have more than one program/erase cycle, so that it can effectively implement a multi-time or few-time programmable array. It would also be desirable for such OTP memory to minimize the overhead cost of implementing an erase operation/erase algorithm and additional die space.
A recent filing by Bisen (US Pub. No. 2013/0265830—incorporated by reference herein) attempts to rectify these kinds of deficiencies in the art. While Bisen proposes a multiple writes with a flash memory cell that uses shifting Vts, he nonetheless still uses an erase circuit which adds complexity and overhead and thus is not a true OTP implementation. Furthermore his scheme suffers from a few drawbacks, including the fact that the data of the system is not erased between program operations, but only at the end when he has run out of available higher Vt states. Bisen simply over-writes his old data while adding new data, meaning that there is some remnant of the prior data, rather than configuring all the data to an initial common state. This can result in potential data breaches, security issues, etc.